voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage‐spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. This article proposes an external capacitor‐less low‐dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. For a 1 μF output capacitor, the maximum output voltage variation to a 0–100 mA load transient with rise and fall times of 10 and 100 ns is only 3 mV, and the PSRR is smaller than −56 dB over the entire load current range. Post-layout simulation results for a 0.35 μm CMOS process design reveal that the proposed LDO requires 59 μA quiescent current at no-load condition and at full-load condition has a current efficiency of 99.8%. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. The CFA consists of an open-loop voltage follower with output local current–current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The circuit does not require any internal compensation capacitor, being stable for a wide range of output load currents and a 1 μF output capacitor. This paper presents a current-steering approach to implement a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) topology. A final benchmark comparison considering all relevant performance metrics is presented. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 ♚. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. This improves the LDO load transient characteristic even at low quiescent current. ![]() Therefore, the slew rate at the gate of pass transistor is enhanced. ![]() Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. ![]() This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier.
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